In many of today's systems, integrated circuits are required to operate with multiple different voltage power supply levels for portions of circuits, such as core logic, analog circuits and input output interfaces, and any other suitable circuits. This multi-voltage (commonly referred to as “split-rail”) requirement is a combination of available power levels, circuit speed requirements, high drive voltage levels, and analog performance requirements. In many scenarios, high voltage supplies with nominal operating voltages that are higher than a transistors over voltage limit are used. An inherent issue with operating multiple voltages is that device voltage over stress can occur causing reliability concerns. For example, gate-junction over stress can be caused by excessive voltages across gate to source or gate to drain junctions, causing gate poly ionic bonds to break down under high electric fields. Drain to source over stress can be caused by high electric fields between the drain to source junction, resulting in impact ionization and punch through break down.
Multi-voltage or split rail circuits may be required, for example, where multiple different power supply voltages may be used by a circuit. For example, on an integrated circuit, core logic may operate at 1.2 volts whereas analog circuits or I/O interfaces on the same integrated circuit may be required to operate at different voltages depending upon the requirements of the system. For example, the analog circuit may be required to operate at 1.8, 3.3 or 5 volt levels. As such, the analog circuits, I/O interfaces or other suitable circuits need to be designed to be able to accommodate the different voltage levels.
A well known technique for overcoming the junction over stresses due to over voltage conditions is the use of series cascode devices, coupled with a limiting bias voltage at a gate of one or more cascoded devices, in order to limit the maximum voltage at the source of the cascode devices. In these scenarios, there is usually a minimum of two different power supply voltage levels that are coupled to the circuit: VDDHI (high voltage power supply level) and VDDLO (low voltage power supply).
During normal operating conditions of the integrated circuit, when both VDDHI and VDDLO have been fully powered up, the use of VDDLO is the limiting voltage on the cascode device to prevent junction over voltage stress. However, higher voltages are often powered up first during system power up to prevent forward conduction of parasitic diodes. As such, VDDHI could have fully ramped to it's nominal operating voltage while VDDLO has yet to begin it's initial ramp up. For this case, no limiting voltage exists on the gate of the cascode device, and the result would be over stress on either the cascode device (NMOS cascode) or the device that is being protected by the cascode transistor (PMOS cascode). As such, thicker gate devices that may use high voltages such as I/O drivers or receivers may require a power supply voltage of 3.3 volts but core logic circuitry may use a lower voltage such as 1.8 volts. When one voltage supply is ramping up and another is at ground level for example, voltage overstress condition of the transistors can occur. In digital to analog converters (DAC) for example such devices may be multi-rail devices. As such multiple simultaneous power supply levels may be used by the device. Sometimes voltage regulators may be off chip and the timing components may be off chip increasing the cost of the system.
A common design work around for this scenario is to require a power up sequencing timing relationship between the ramp up of the VDDHI and VDDLO voltage levels in order to limit the maximum voltage difference between the VDDHI and VDDLO at any time. However, this can result in unnecessary delays in circuit operation. Another method that is used is the use of a series diodes between the two power supply voltages such that their voltage difference does not exceed the diode strong voltage drop. Although helpful, these common prior art solutions may present complexity in the system by requiring for example a BIOS, or other component to control the power up sequencing timing, or can increase the discrete component board space requirements due to the additional diode configurations.
It would be desirable in one case to, among other things, provide an on chip solution that may provide an adequate cascode device bias voltage for the differing bias states during power ramp up, independent of the timing between the ramp up of the differing power voltages. All that may be needed is that the higher voltage may ramp up first, but no specific timing requirements between the ramps would be needed.